(a) Field of the Invention
The present invention relates to a semiconductor memory, and more particularly it pertains to a high-speed and high-density semiconductor memory.
(b) Description of the Prior Art
Semiconductor memories are under development of higher integration density and larger capacity. In random access memories (RAM), the density of 16 kilobits per chip is now popular. As the integration density has increased to such a level, a reduction in the surface occupation area per memory cell will be required accordingly. In most of the 4 kilobit RAM's, one memory cell is formed with one lateral transistor structure, which in most of the 16 kilobit RAM's, the transistor structure is further simplified into the charge coupled type. In both cases, the basic concept or the equivalent circuit of a memory cell is "one transistor per memory cell" and this will not be simplified further. Namely, in a memory cell, there is a region for storing information, another region for extracting this information to the outside of the cell, and a further region between these two for controlling (or at least helps controlling) the transfer of the memory. Then, the integration density of memory cells in a semiconductor memory is determined largely by the surface occupation area of one transistor or the like which works as a memory cell. The so-called MOS FET type memory cell and the charge coupled device type memory cell can be roughly classified as the surface structure cell which inevitably accompany relatively large surface occupation area. Furthermore, since the electron and the hole mobilities in the surface of a semiconductor body (surface mobilities) are usually lower than those in the bulk (bulk mobilities) due to various surface state such as trapping levels (for example in silicon the surface mobility is about one third to one fifth of the bulk mobility), the carrier transit time becomes low in the surface region and the high speed-operation is at least partially limited thereby.
The inventor of the present invention has proposed a new type of field effect transistor (now called "static induction transistor") which has a low series (source to intrinsic gate) resistance and can show non-saturating drain current versus drain voltage characteristics disclosed in his U.S. patent application Ser. Nos. 817,052 and 576,541, and stated in "IEEE Trans. Electron Devices" ED-22, 185 (1975). The static induction transistor has many advantages such as that the parasitic gate (source-gate and gate-drain) capacitance is very small, that the gate region resistance can be very low, that charge carriers are drifted by an electric field and that the space charge storage effect is very small. Therefore, the application of the static induction transistor is of much interest in various fields. However, although some developments in the integrated circuits by the use of the static induction transistor have been made and proposed, there still is hardly any proposal with respect to the memory device.